Auto Page CPX-3600 manuals

Auto page CPX-3600 User Manual (7 pages)

Brand: Auto-page | Category: Security access control systems | Size: 0.08 MB |

English

Table of contents

C a r - P r o ®

1

TRANSMITTER OPERATION

3

A L AR M IN D I CA T O RS

7

Auto page CPX-3600 Specifications (243 pages)

Brand: Auto-page | Category: Security access control systems | Size: 2.33 MB |

English

Table of contents

ST72321xx-Auto

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Contents

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1 Description

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ST72321xx-Auto Description

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2.1 Package pinout

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2.2 Pin description

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4 Flash program memory

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4.4 ICC interface

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4.7 Related documentation

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5.1 Introduction

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5.2 Main features

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5.3 CPU registers

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5.3.1 Accumulator (A)

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5.3.3 Program counter (PC)

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Interrupt management bits

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6.1 Introduction

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6.2 Main features

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6.3 Phase locked loop

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6.4 Multi-oscillator (MO)

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Crystal/ceramic oscillators

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Internal RC oscillator

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6.5.1 Introduction

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6.5.5 Internal watchdog RESET

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Monitoring the V

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main supply

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6.6.3 Low power modes

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6.6.4 Interrupts

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SICSR description

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Application notes

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7 Interrupts

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Servicing pending interrupts

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Non-maskable sources

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Maskable sources

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HARDWARE PRIORITY

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7.6 External interrupts

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Interrupts ST72321xx-Auto

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ST72321xx-Auto Interrupts

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8 Power saving modes

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8.3 Wait mode

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8.4.1 Active Halt mode

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8.4.2 Halt mode

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Halt mode recommendations

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9 I/O ports

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9.2.2 Output modes

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9.2.3 Alternate functions

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1. The diode to V

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ST72321xx-Auto I/O ports

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9.3 I/O port implementation

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9.4 Low power modes

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9.5 Interrupts

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10 Watchdog timer (WDG)

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10.5 Low power modes

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10.8 Interrupts

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10.9 Register description

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(MCC/RTC)

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Low power modes

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Interrupts

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12.2 Functional description

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12.2.8 Input capture function

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12.3 ART registers

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13 16-bit timer

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13.3 Functional description

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16-bit timer ST72321xx-Auto

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16-bit read sequence

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13.3.2 External clock

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13.3.3 Input capture

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13.3.4 Output compare

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13.3.6 One Pulse mode

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Procedure

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13.4 Low power modes

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13.5 Interrupts

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13.6 Summary of timer modes

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13.7 16-bit timer registers

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ST72321xx-Auto 16-bit timer

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Related documentation

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14.1 Introduction

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14.2 Main features

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14.3 General description

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14.3.1 Functional description

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14.3.3 Master mode operation

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14.3.5 Slave mode operation

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CPHA = 1

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CPHA = 0

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14.5 Error flags

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14.5.4 Single master systems

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14.6 Low power modes

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14.7 Interrupts

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14.8 SPI registers

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15.3 General description

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Figure 62. SCI block diagram

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15.4 Functional description

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15.4.2 Transmitter

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15.4.3 Receiver

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Extended baud rate generation

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Parity control

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SCI clock tolerance

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Clock deviation causes

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Noise error causes

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15.5 Low power modes

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15.6 Interrupts

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15.7 SCI registers

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16.3 General description

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16.3.3 SDA/SCL line control

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16.4 Functional description

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16.4.2 Master mode

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Slave address transmission

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Master receiver

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Master transmitter

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Error cases

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16.5 Low power modes

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16.6 Interrupts

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16.7 Register description

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16.7.2 I

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C status register 1 (SR1)

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16.7.3 I

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C status register 2 (SR2)

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16.7.4 I

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16.7.5 I

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C data register (DR)

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16.7.6 I

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C own address register (OAR1)

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16.7.7 I

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C own address register (OAR2)

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Table 90. I

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17.1 Introduction

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17.2 Main features

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17.3 Functional description

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17.4 Low power modes

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17.5 Interrupts

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17.6 ADC registers

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17.6.2 Data register (ADCDRH)

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17.6.3 Data register (ADCDRL)

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18 Instruction set

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18.1.1 Inherent

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18.1.2 Immediate

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18.1.3 Direct

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18.1.5 Indirect (short, long)

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18.2 Instruction groups

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18.2.1 Using a prebyte

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19 Electrical characteristics

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19.3 Operating conditions

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IT+(LVD)

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Power consumption vs f

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: Flash devices

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19.5.1 General timings

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19.5.2 External clock source

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19.5.5 PLL characteristics

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19.6 Memory characteristics

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19.9.1 Asynchronous RESET pin

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19.9.2 ICCSEL/V

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ICCSEL/V

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PROGRAMMING

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19.11.2

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±5% tolerance

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±2% tolerance

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INJ(PIN)

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19.12.3 ADC accuracy

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20 Package characteristics

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21.1.1 Flash configuration

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21.3 Development tools

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21.4 ST7 application notes

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22 Known limitations

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22.1.8 16-bit timer PWM mode

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22.2 All Flash devices

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23 Revision history

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